How Does the Separate Cache Die Improve Performance?
Fujitsu presented its new 144-core Monaka server processor at the Hot Chips 2026 conference on August 24, revealing an Arm-based chip that stacks its entire cache on a separate 5nm die. The design aims to boost performance and efficiency for data center workloads by reducing latency and improving bandwidth. This marks the first public disclosure of the Monaka architecture’s key innovations.
Breaking news
Judge Questions Fairness of Google's AI Overviews in Antitrust Case
Apple's iPhone Event Tagline Varies by Country Ahead of September Launch
Gemini 3.5 Transcribe Eliminates Filler Words From Speech
Google addresses Keep list addition issues with potential fixThe Monaka CPU features a narrow 256-bit SVE2 vector unit, a departure from wider implementations seen in competing Arm server chips. Fujitsu engineers explained that this width balances computational throughput with power efficiency, particularly for mixed workloads involving AI, scientific computing, and cloud services. The separate cache die, manufactured on TSMC’s 5nm process, is bonded to the main compute die using advanced 3D packaging. This allows the cache to run at higher speeds and operate independently of the core complex’s thermal envelope. The chip is rated at 350W thermal design power, targeting high-density server environments.
By isolating the cache on its own die, Fujitsu reduces signal travel distance and minimizes interference between logic and memory circuits. This separation enables the cache to be optimized for speed without being constrained by the heat generated by the 144 cores. Engineers noted that the design allows for larger cache capacities per core while maintaining low access latency, which is critical for database and virtualization tasks. The 5nm process also provides better transistor density and lower leakage compared to older nodes used in prior generations.
What Trade-Offs Come with the 256-bit SVE2 Width?
Fujitsu chose 256-bit SVE2 vectors to avoid the diminishing returns of wider units in real-world software, where vectorization efficiency often drops below peak theoretical performance. The company stated that wider vectors would increase power consumption and circuit complexity without proportional gains in many server applications. Instead, the 256-bit width supports efficient execution of mixed instruction streams, including scalar and vector code, while simplifying compiler optimization. This approach aligns with Fujitsu’s focus on sustained performance over bursty peak metrics.
The Monaka CPU is expected to power Fujitsu’s next-generation PRIMERGY server line, with sampling planned for early 2027. Analysts suggest the chip could challenge x86 dominance in hyperscale and HPC markets if software support matures. Its success will depend on ecosystem readiness, particularly Linux kernel optimization and Arm-native software availability. Fujitsu emphasized that Monaka is part of a broader strategy to deliver differentiated Arm-based solutions for energy-efficient computing.
Frequently Asked Questions
What is the significance of stacking the cache on a separate die? Stacking the cache on a separate 5nm die allows Fujitsu to optimize memory performance independently of the core complex, reducing latency and improving bandwidth while managing thermal and power constraints more effectively.
Why did Fujitsu limit the SVE2 width to 256 bits instead of going wider? Fujitsu found that wider vector units offer limited real-world benefits due to software inefficiencies, and a 256-bit width provides a better balance of performance, power, and complexity for typical server workloads.
When will the Monaka CPU be available in commercial systems? Fujitsu plans to begin sampling the Monaka processor to customers in early 2027, with integration into its PRIMERGY server lineup expected shortly after.
